Performances of components composing computers and other information processing equipment have made great advancement, as seen in memory, processor and switching LSI (large-scale integrated circuit). In view of improving system performances, it is necessary to improve not only performances of the individual components, but also signal transmission rate between these components or elements (increase in transmission capacity and reduction in transmission delay). For example, improvement in performances of computer (server) needs improvement in the signal transmission rate between a memory, such as SRAM (static random access memory) or DRAM (dynamic random access memory), and a processor, and signal transmission rate between servers. Besides the servers, with the progress in performances of information processing equipment including those for backbone system of communication, there has been a growing need of increasing data rate in signal transmission inside and outside the equipment.
In recent years, in addition to a demand on increase in the data rate, there has been a further demand of implementing such higher data rate at a low power consumption. In order to respond to the requirements of higher data rate and lower power consumption, not a few integrated circuits have encountered need for increasing the data rate of an input/output circuit (I/O) from several gigabits/second to several tens gigabits/second. For advanced equipment, it is also necessary to integrate a large number of I/O ports compatible to such large data rate into a single integrated circuit. High speed I/O needs a large number of analog circuits including equalizer, timing generator and so forth. From the viewpoints of readiness in design and integration of a large number of I/Os, it is preferable to replace these analog circuits with digital circuits.
There has been known a data decoding circuit which includes an analog-digital converter converting input analog signals expressing a data stream into digital signals in synchronization with a clock signal, to thereby generate a digital code stream obtained by sampling with intervals shorter than data intervals of the data stream; a phase detector calculating a position of cross point at which a line segment obtained by interpolating the digital data stream crosses the horizontal line expressing the level of predetermined code value, lying approximately at the center of a possible range of values of digital codes; a phase estimation unit determining an estimated position of the center point of the data stream based on the position of the cross point; and a data decision unit extracting a stream of decided data value from the digital data stream, based on the position of the cross point and the estimated position of the center point of the data stream (see Patent Document 1).
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2010-130366